One conventional way of receiving 3.3V input signals in 1.8V integrated circuit technology is to use an n-type metal-oxide-semiconductor (NMOS) device to down level-shift the input signal so that it does not damage the receiver (which is designed using a 1.8V technology, i.e., the receiver is adapted to deal with 1.8V input signals without damage). FIG. 1, for example, is a schematic diagram illustrating a portion of an exemplary integrated circuit 100 in which a pass gate 102 (e.g., an NMOS transistor) is placed in the current path between an input/output (IO) pad 104 and a receiver (RX) 106. The IO pad receives an input signal of 3.3V, while the receiver 106 is designed to receive a high voltage of no more than 1.8V. The gate of the NMOS transistor is connected to a bias voltage (bias) that ensures that no devices see more than the reliability limit of 1.8V on the terminals.
This solution, however, has trouble supporting the low voltage differential signaling (LVDS) standard. For instance, the pass gate 102 cannot drive the input signal to the receiver when the input signal is a high common-mode signal or a low voltage complementary metal-oxide-semiconductor 18 (LVCMOS18) signal. One conventional way to solve this problem is to add a PMOS device to the pass gate in parallel with the NMOS device. FIG. 2, for example, is a schematic diagram illustrating a portion of an exemplary integrated circuit 200 in which a pass gate 202 (i.e., an NMOS transistor in parallel with a PMOS transistor) is placed in the current path between an IO pad 204 and a receiver (RX) 206. Both the NMOS and PMOS transistors are turned on only when supporting standards of 1.8V and below, while the PMOS transistor is turned off when the receiving standard is higher than 1.8V.